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STRUCTURE PRODUCT SERIES TYPE BLOCK DIAGRAM PACKAGE PIN ASSIGNMENT Functions
Silicon Monolithic Integrated Circuit 4-Channel Switching Regulator Controller for Digital Camera
Fig. 1 Fig. 2 Fig. 3
Contains cross converter(1ch), step-down converter(2ch), step-up converter(1ch), configurable for inverting/step-down converter(1ch). 2channels contain transistor for synchronous rectifying action mode. 1channels contain FETs for the step-up converter. All channels contain internal compensation. It is possible separately control all channel Operating frequency 1.5MHz(CH2), 750kHz(CH1,3,4). Contains output interception circuit when over load. 1 channels have high side switches with soft start function. 3.3mmx3.3mm t = 0.55mm WLCSP package (VCSP50L3)
Absolute maximum ratings (Ta=25)
Parameter Symbol Limit Unit
VCC 0.37 V VHx12 0.37 V HS4H 0.37 V Power Input Voltage VLx4 0.322 V VDCM3 150.3 V IomaxHx1 +2.0 A IomaxHx2 +1.0 A Output Current IomaxHS4 +1.2 A IomaxLx4 1.0 A Power Dissipation Pd 1325(*1) mW Operating Temperature Topr 25+85 Storage Temperature Tstg 55+150 Junction Tempareture Tjmax +150 (*1) When mounted on a glass epoxy PCB (50 mm x 58 mm x 1.75 mm). Reduced by 10.6 m W/C when using at Ta = 25 C or higher.
Power
Supply
Voltage
Recommended operating conditions
Parameter Power Supply Voltage VREF Pin Connecting Capacitor VREGA Pin Connecting Capacitor Symbol Limit
MIN 2.5 0.47 0.47
TYP 1.0 1.0
MAX 5.5 4.7 4.7
Unit
VCC CVREF CVREGA
V F F
Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority.
REV. B
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Electrical characteristicsTa=25, VCC=3.0V, STB14=3V
Parameter Symbol MIN 2.4 Limit TYP 2.5 MAX 2.6 Unit Conditions Parameter Output Driver V Io=5mA CH1 LX11 terminal Highside SW ON Resistance CH1 LX11 terminal Lowside SW ON Resistance CH1 LX12 terminal Highside SW ON Resistance CH1 LX12 terminal Lowside SW ON Resistance CH2 Highside SW ON Resistance CH2 Lowside SW ON Resistance CH3 Driver Output voltage H CH3 Driver Output voltage L CH4 NMOS SW ON Resistance CH4 Load SW ON Resistance Discharge switch IINV VINV1 0.79 0 0.80 50 0.81 nA V INV14, NON3=3.0V CH1, 2, 4 CH3discharge SW ON Resistance RDCM 82 165 330 RON11P 120 200 m Hx1=3.0V Symbol MIN Limit TYP MAX Unit Conditions
Internal Regulator VREGA Output Voltage VREGA Prevention Circuit of Miss Operation by Low voltage Input Threshold Vstd2 Voltage Hysteresis Vstd1 Width Short Circuit Protection SCP Tscp detect time Timer start threshold Vtcinv voltage Oscillator Frequency CH2 Frequency CH1,3,4 Max duty CH1 LX11 Max duty CH1 LX12 Max duty 2 step-down Max duty 3,4 Error Amp Input Bias current INV threshold 1 CH3 Output Voltage Line Regulation Output Current When Shorted Soft start CH1 Soft Start Time CH2 Soft Start Time CH3 Soft Start Time CH4 Soft Start Time Tss1 Tss2 Tss3 Tss4 2.6 0.6 2.6 2.6 3.5 0.9 3.5 3.5 4.4 1.2 4.4 4.4
msec msec msec msec
2.25 50
2.3 100
2.35 150
V mV
VCC Monitor
RON11N
-
130
210
m
VCC=3.0V
RON12P
-
120
200
m
VOUT1=3.0V
20 0.38
25 0.48
30 0.58
ms V Monitor CH2
INV
RON12N RON2P RON2N Vout3H Vout3L RON4N RON4P
VCC -1.5 -
100 250 250 VCC -1.0 0.5 500 250
160 400 400 1.0 800 350
m m m V V m m
VCC=3.0V Hx2=3.0V VCC=3.0V IOUT3=-50mA ,NON3=0.2V IOUT3=50mA NON3=-0.2V VCC=3.0V HS4H=3V , VCC=3.0V
fosc1 fosc2 Dmax11 Dmax12 Dmax2 Dmax3,4
1.2 0.6 86 86
1.5 0.75 92 92
1.8 0.9 100 96 100 96
MHz MHz % % % %
Switch to configure Inverting/Step-down IDSEL Control voltage Step down Inverting
VIDDO VIDIN
For Inverting Base Bias Voltage Vref VOUT3 DVLi Ios -7.105 0.2 -7.00 4.0 1.0 -6.895 12.5 V mV mA VCC=2.85.5V Vref=0V
VCC x0.7 0
-
VCC VCC x0.3
V V
(1) (1)
STB14 STB Control voltage Active Not Active VSTBH1 VSTBL1 RSTB1 1.5 -0.3 250 400 5.5 0.3 700 V V k
Pull down Resistance Circuit Current VBAT terminal Hx terminal Stand-by Current L terminal HS4H terminal Circuit Current VCC current when voltage supplied for the terminal
ISTB1 ISTB2 ISTB3 ISTB4
-
-
5 5 5 5
A A A A INV1 4=1.2V , NON3=-0.2V Step down Step up
Icc
-
2.0
4.0
mA
(1)The input of IDSEL terminal is CMOS inverter input that makes VCC a power supply.
Please connect to either of GND or VCC for irregular prevention. This product is not designed for normal operation with in a radioactive environment
REV. B
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Block Diagram
Package BD9352
LOT No.
(UNIT : mm)
Fig. 2
Exposing the package to strong light like the strobe will cause incorrect operation of the device. Please confirm the operation after measure of shading so that light should not enter.
Fig. 1
Pin No. A1,B1 A2 Pin Name GND HX2 LX2 PGND2 HX1 INV2 STB2 STB1 STB3 LX11 VCC VREGA STB4 PGND1 HS4H INV4 IDSEL LX12 HS4L VREF3 NON3 I NV3 I NV1 VOUT1 TEST1 LX4 PGND34 OUT3 DCM3 TEST2 Functions Ground terminal CH2 Input terminal for synchronous High side switch, Power supply for Pch Driver CH2 Terminal for connecting inductors CH2 Ground terminal for internal FET CH1 Input terminal for synchronous High side switch, Power supply for Pch Driver CH2 Error AMP inverted input CH2 ON/OFF switch CH1 ON/OFF switch CH3 ON/OFF switch Terminal for connecting inductor for CH1 input Input for battery voltage VREGA Output CH4 ON/OFF switch CH1 Ground terminal for internal FET CH4 Power supply for internal load switch CH3 Error AMP inverted input CH3 Inverting /Step down mode selector L : Inverting, H : Step down Terminal for connecting inductor for CH2 output CH4 Power supply for internal load switch CH3 base bias voltage CH3 Error AMP non-inverted input CH3 Error AMP inverted input CH1 Error AMP inverted input CH1voltage output terminal TEST terminal. Please short GND or OPEN CH4 Terminal for connecting inductors Ground terminal for CH3 driver and CH4 internal FET Terminal for connecting gate of CH3 PMOS CH3 output voltage discharge terminal. When you don't use discharge function, please short GND terminal. TEST terminal. Please short GND or OPEN
Pin Assignment
A3 A4 A5, A6
1 A GND
2 HX2
3 LX2
4 PGND2
5 HX1
6 HX1
B2 B3 B4 B5 B6 C1
B
GND
INV2
STB2
STB1
STB3
LX11
C2 C5 C6 D1 D2 D5
C
VCC
VREGA
STB4
PGND1
D
HS4H
INV4
IDSEL
LX12
D6 E1 E2 E3 E4 E5 E6
E
HS4L
VREF3
NON3
INV3
INV1
VOUT1
F
TEST1
LX4
PGND34
OUT3
DCM3
TEST2
F1 F2 F3 F4 F5 F6
Fig. 3
REV. B
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Operation Notes
.) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. .) GND potential Make sure GND is connected at lowest potential. All pins except NON3, must not have voltage below GND. Also, NON3 pin must not have voltage below - 0.3V on start up. .) Setting of heat Make sure that power dissipation does not exceed maximum ratings. .) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. .) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. .) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. .) Voltage of STB pin The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V. The region between 0.3V and 1.5V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01F. .) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. .)Light sensitivity Exposing the package to strong light like the strobe will cause incorrect operation of the device. Please confirm the operation after measure of shading so that light should not enter. .)IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.4): When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal.
Resistor Terminal A
Transistor (NPN) B E Terminal B C GND N Terminal Parasitic element N GND
P N N
P
P N Parasitic element
P N
P P-board
P
P-board
Parasitic l t
GND
Fig - 4 Simplified structure of a Bipolar IC
REV. B

Notice
Notes
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